The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d) delay locked loops (xe2x80x9cDLLxe2x80x9d). More particularly, the present invention relates to an integrated circuit delay locked loop design and method for controlling the same of especial utility in double data rate (xe2x80x9cDDRxe2x80x9d) dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) devices, static random access memory (xe2x80x9cSRAMxe2x80x9d) devices, integrated circuit (xe2x80x9cICxe2x80x9d) processors and other IC devices.
DDR DRAM device functionality is specified by a Joint Electron Devices Engineering Counsel (xe2x80x9cJEDECxe2x80x9d) standard and such memories are able to achieve this effective doubling of the device""s bandwidth by inclusion of DLL circuitry to achieve synchronization of data accesses at a point in time to enable the reading of data on both the rising and falling edges of each clock cycle. In such DLL circuits, a phase detector is utilized to determine the relative phase between two clock signals, such as the system clock and synchronization (xe2x80x9csyncxe2x80x9d) clock signal in a DDR memory device.
In certain delay locked loops, the frequency range for locking of the loop can be limited by power supply voltage levels because the reference clock comparison is not matched to the total delay in the programmable delay section. Moreover, the generation of controlling voltages for the programmable delay portion of the loop can be limited by the overlap of phase detector outputs.
Disclosed herein is a low power consumption phase locked loop for integrated circuit devices wherein a wider frequency range of operation is achieved by matching the delay of the clock comparison function of the phase detector to the slow operating condition of the programmable delay. In a particular embodiment disclosed herein, this may be effectuated by incorporating at least one additional flip-flop section in the phase detector circuit and more than one such section may be utilized depending on the operating targets of maximum frequency and frequency range. Operationally, the primary point of interest is at power up or reset bias conditions.
By latching the phase detector outputs through the use of a fast/slow latch circuit, a minimum control pulse is defined which allows a unitized change on the voltage signals that control the programmable delay in a voltage controlled delay line. This also improves efficiency and reduces power consumption by eliminating switching current through transistors that control the voltage levels determining the programmable delay.
Functionally, the first two reference clock pulses on the CLOCK input to the phase detector are effectively ignored through the use of the flip-flop section. This results in a programmable delay change in a slower direction for most operating conditions in order to achieve lock and, overall, effectively improves the range of frequencies for which lock can be achieved. The phase detector outputs are logically exclusive OR""d then latched by a fast/slow latch circuit to provide clean digital xe2x80x9cspeed upxe2x80x9dor xe2x80x9cslow downxe2x80x9d signals to the delay voltage control circuit. By eliminating the conventional overlap of these inputs to the delay voltage control circuit, only one directional change (i.e. xe2x80x9cspeed upxe2x80x9d or xe2x80x9cslow downxe2x80x9d) occurs per cycle. This eliminates the potential for excessive, or wasted, current consumption caused when overlapping signals are used while also allowing the control voltages to go all the way to supply or circuit ground levels.
Particularly disclosed herein is a delay locked loop circuit which comprises a phase detector coupled to receive first and second clocking signals and producing at least one output signal indicative of a phase relationship between the first and second clocking signals. A latch circuit is coupled to receive the output signal and produces at least one fast/slow signal in response thereto. A voltage controlled delay line is coupled to receive the fast/slow signal and produce the second clocking signal for input to the phase detector.
Also disclosed herein is a method for operating a delay locked loop comprising the steps of: inputting a first clock signal to the delay locked loop; comparing the phase of the first clock signal to the phase of a second clock signal; producing at least one output signal indicative of the phase relationship between the first and second clock signals; latching the output signal to provide at least one fast/slow signal in response thereto and controlling a delay line in response to the fast/slow signal to produce the second clock signal.